求教ALLEGRO 做 database check出错

********************************************************************************
*  Performance checking for design G:/My project/TSQ-8A/PCB/TSQ-8A.brd
********************************************************************************
Ratsnest schedule check
-------------------------------
* OK.
DRC check
----------------------
* The number of physical/spacing csets is 0.080000 larger than the number
  of nets Suggest examining constraint model.
  ISSUE: Misuse of the Allegro constraint model such as using a spacing
         cset for each diffpair in the design. Result is system
         performance degradation.

Constraint region check
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* OK.
Dynamic shape check
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* OK.
Sector table check
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* The ratio of design extent to route keepin extent is too large (50.050670). Suggest reducing design extent.
Constraint set check
---------------------------------
* OK.
NODRC_SYM_SAME_PIN check
---------------------------------
* OK.
Cross section check for bad dielectric constant values
--------------------------------------------------------
* OK.
Padstack size check
---------------------------------
* OK.

2 problems found.        0 maintenance problems found.

是约束规则设置不对吗?