- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
PCB 导入网表出错，但是又不知道是什么错误...
录入：edatop.com 点击：
错误信息显示如下。求大神帮我解释一下。万分感谢~~
- (---------------------------------------------------------------------)
- ( )
- ( Netrev Allegro Import Logic )
- ( )
- ( Drawing : SDX_Allegro.brd )
- ( Software Version : 16.3p004 )
- ( Date/Time : Fri Dec 14 07:39:06 2012 )
- ( )
- (---------------------------------------------------------------------)
- ------ Directives ------
- RIPUP_ETCH FALSE;
- RIPUP_SYMBOLS ALWAYS;
- Missing symbol has error FALSE;
- SCHEMATIC_DIRECTORY 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO';
- BOARD_DIRECTORY '';
- OLD_BOARD_NAME 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/SDX_Allegro.brd';
- NEW_BOARD_NAME 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/SDX_Allegro.brd';
- CmdLine: netrev -$ -i D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO -y 1 D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/#Taaaaaa05284.tmp
- ------ Preparing to read pst files ------
- #1 ERROR(24) File not found
- Packager files not found
- #2 ERROR(102) Run stopped because errors were detected
- netrev run on Dec 14 7:39:06 2012
- COMPILE 'logic'
- CHECK_PIN_NAMES OFF
- CROSS_REFERENCE OFF
- FEEDBACK OFF
- INCREMENTAL OFF
- INTERFACE_TYPE PHYSICAL
- MAX_ERRORS 500
- MERGE_MINIMUM 5
- NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
- NET_NAME_LENGTH 24
- OVERSIGHTS ON
- REPLACE_CHECK OFF
- SINGLE_NODE_NETS ON
- SPLIT_MINIMUM 0
- SUPPRESS 20
- WARNINGS ON
- 2 errors detected
- No oversight detected
- No warning detected
- cpu time 0:00:46
- elapsed time 0:00:00
没有设置库路径
嗯，应该是封装库的问题
库的路径不对
请问可以检测出具体是哪几个元件没有对应的封装么?库路径已经设置了啊
请问可以检测出具体是哪几个元件没有对应的封装么?库路径已经设置了啊
请问可以检测出具体是哪几个元件没有对应的封装么?库路径已经设置了啊
小编的问题是，网表的路径没有指对应。读取不到网表信息啊，当然会出错。
应该是，你导入的网表，不对；
或说你导入的网表路径不对；
你仔细看看，
应该是这个问题，
我之前碰到过，
谢谢~~~确实是网络路径不对...
Thankyou ...真的是网表路径不对...
