Interconnect Cap Verification of Cadence Layout with CST MWS

Does anyone know how to import a Cadence GDSII/dxf file into CST Microwave Studio to perform a verification of the interconnect capacitance.

I don't trust the results of Assura and I would like to verify the results with a 3D EM simulator.

Should I draw everything again by hand or is there a way to directly import the extracted design ? ( If not CST MWS then Momentum or Sonnet ? )

Hello,

Yes you can directly import the GDSII/DXF layout data into Sonnet using Import options & then setup the dielectric layer & metalization details & simulate...
Even it directly interfaces to Cadence Virtuoso...

http://www.sonnetsoftware.com/produc..._cvbridge.html

---manju--

Here's a description of the design flow for Sonnet within the Cadence RFIC environment:

http://www.muehlhaus.com/files/Sonne..._EEEfCOM09.pdf

See page 15 ff for a design flow overview with some screenshots.

For interconnect/lines, you might want to use the RLCG model (called "mtline" in Spectre). On page 43 ff, there is a description hot to get create that output data.

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