状态机举例

状态机举例

你可以指定状态寄存器和状态机的状态。以下是一个有四种状态的普通状态机。
// These are the symbolic names for states
// 定义状态的符号名称
parameter  [1:0]
  S0 = 2'h0,
  S1 = 2'h1,
  S2 = 2'h2,
  S3 = 2'h3;
// These are the current state and next state variables
// 定义当前状态和下一状态变量
reg [1:0] state;
reg [1:0] next_state;

// state_vector state
// 状态向量的转移关系
always @ (state or y or x)
begin
  next_state = state;
  case (state)                
    S0: begin
      if (x) begin
        next_state = S1;
      end
      else begin
        next_state = S2;
      end
    end
    S1: begin
      if (y) begin
        next_state = S2;
      end
      else begin
        next_state = S0;
      end
    end
    S2: begin
      if (x & y) begin
        next_state = S3;
      end
      else begin
        next_state = S0;
      end
    end
    S3: begin
      next_state = S0;
    end
  endcase
end

always @ (posedge clk or posedge reset)
begin
  if (reset) begin
    state <= S0;
  end
  else begin
    state <= next_state;
  end
end

　　同样的状态机也可以用下面的代码以“One hot”编码方式实现。

// These are the symbolic names for states // 定义状态的符号名称 parameter [1:0] S0 = 2'h0, S1 = 2'h1, S2 = 2'h2, S3 = 2'h3; parameter [3:0] s0 = 4'h1, s1 = 4'h2, s2 = 4'h4, s3 = 4'h8; // These are the current state and next state variables // 定义当前状态和下一状态变量 reg [3:0] state; reg [3:0] next_state; // state_vector state // 状态向量的转移关系 always @ (state or y or x) begin next_state = state; case (1) state[S0]: begin if (x) begin next_state = 1 << S1; end else begin next_state = 1 << S2; end end state[S1]: begin if (y) begin next_state = 1 << S2; end else begin next_state = 1 << S0; end end state[S2]: begin if (x & y) begin next_state = 1 << S3; end else begin next_state = 1 << S0; end end state[S3]: begin next_state = 1 << S0; end endcase end always @ (posedge clk or posedge reset) begin if (reset) begin state <= 1 << S0; end else begin state <= next_state; end end