搭建10位理想ADC的问题

小弟搭建了一个10bit-DAC，为了仿真，调用“ahdlLib”库的“adc_8bit_ideal”，输出端为vd0-vd7,将里面的Veriloga代码做修改后得到10bit的理想ADC，并修改symbol，输出端为vd0-vd9，仿真时系统提示vd8和vd9：“cannot be found in the switched master of the instance”，请各位指点，不胜感激。

try delete the symbol, then change the verilog A, say, add one space anywhere, then close and save, see if it prompts you to generate a symbol view. If not, you need to edit the cdf parameter from CIW window.

Using the methord you provide,I  have solved the problem. Thank you very much.

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