bandgap can't work in post-simulation

i have designed a bandgap (opamp+bjt), in pre-simulation, the DC/AC/TRAN are all ok; but in post-simulation, the output of bandgap is only a few mV lower than vdd, when vdd is 2.1V,it is 2V.it should have to be adjacent to 1.2V in pre-simulation; i checked the simulation result, i found that, the voltage difference between positive and negative end of opamp is about 100mV (so big difference, only 10uV for pre-simulation), i think maybe it is the reason.
     later, i used non-parasitic post-layout netlist (NO RC or ONLY R, just like pre-simulation netlist), but i get the right result, so my layout have problems,but DRC and LVS have both passed,How can I correct my problem? or any other reasons? can anyone have met the same problem? or any advice?
    Thank you in advance.

Check parasitic caps list, there is a big one, which delayed the circuit's start-up.
Give more time to the post tran simulation, or dig out the big cap.

    my start-up has the problem you say when I pin out start-up voltage, Thanks for your reply

八成是你 提取寄生参数的 规则文件有问题，你自己看看提取后的网标，看看Bipolar或者电阻之类器件写的对不对。

how about checking you pre-sim at some corner condition?

    规则文件没问题啊，后仿出来的网标我也看了，和电路是一致的

    I did the sims separately and compare their waves.

    后仿真网表中BJT或者DIODE有无面积?如果有面积的话仿真软件可能不认，仿真结果会错的。

删掉后仿真网表中BJT管的"area=?",保留“m=?”，如果其他流程正常，后仿应该就正常工作了。

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