Dual loop CDR (clock data recovery) used in high speed transceiver
录入：edatop.com 阅读：
Hi, i am currently working on dual loop CDR design architecture used in the high speed transceiver. Mostly of the time, i am referring to the IEEE paper but hardly to understand all maybe i am still a beginner to CDR design. Can somehow show me where can i download a good reference book discussing about CDR? One more thing to ask is that what will make the chip to have high bit error rate?
I am also searching this topic. Please tell me if you get any information.
me too ,thank you！
so far no response
KAN KAN
Reply 1 # kkliaw77
Needgodfatherhelp
申明：网友回复良莠不齐，仅供参考。如需专业解答，请学习本站推出的微波射频专业培训课程。
上一篇：cadence中的错误怎么解决
下一篇：上海做芯片反剖的公司谁知道有哪些
