tsmc0.25工艺做calibre的lvs，原理图netlist不识别电容，管子类型
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电阻做lvs可以通过，而电感，电容和管子做lvs时却提示原理图和版图对不上，后来发现layout输出的网表可以识别器件类型，而schematic的输出的网表却不能识别器件类型，所以老是对不上，麻烦各位大侠指点一下问题出在那里喔，不胜感激！
您好，这是提示的错误，我看了一下schematic和layout里面的model都是nmos_rfw5，是一样的啊，呵呵
是不是，原理图的MODEL名字与版图提出来的器件MODEL名字不一样，才对不上，最好把error信息，也贴下啊
您好，这是提示的错误，我看了一下schematic和layout里面的model都是nmos_rfw5，是一样的啊，呵呵
1) 把lvs.rep报告贴出来
2）把shcematic 产生的CDL网表贴出来
这是报出来的lvs.report
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: delete.lvs.report
LAYOUT NAME: /home/cwjia/lna_tsmc025/delete.sp ('delete')
SOURCE NAME: /home/cwjia/lna_tsmc025/delete.src.net ('delete')
RULE FILE: /home/cwjia/lna_tsmc025/_calibre.lvs_
CREATION TIME: Thu Sep 13 01:50:40 2012
CURRENT DIRECTORY: /home/cwjia/lna_tsmc025
USER NAME: cwjia
CALIBRE VERSION: v2009.1_17.14 Mon Feb 16 12:59:40 PST 2009
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT delete delete
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "AVDDBG" "AVDDR" "AVDWELL" "VDWELL" "VD33APST" "VDD5V" "TAVD33" "VD33PST" "AVDD" "TAVDD"
"TAVD33PST" "TAVDDPST" "AVD33B" "VDD" "AVD33G" "DVDD" "AVDDG" "AVDDB" "VDDG" "VDDPST"
"VD33REF" "VD33" "AVD33R" "VDDSA"
LVS GROUND NAME "VSSPST" "AVS33R" "AVSSUB" "VSSREF" "VSSAPST" "VS33APST" "DVSS" "AVS33G" "AVSSBG" "TAVSS"
"AVS33B" "AVSSB" "GND" "VSSG" "VSSUB" "VSS" "AVSS" "TAVSSPST" "AGND" "AVSSR" "AVSSG"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES NO
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 65536
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTION AB RC RE RG
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE rppoly_rf PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppoly_rf SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppolywo_rf PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppolywo_rf SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCTION PRIORITY PARALLEL
// Trace Property
TRACE PROPERTY mn(nm) l l 2
TRACE PROPERTY mn(nm) w w 2
TRACE PROPERTY mn(n1) l l 2
TRACE PROPERTY mn(n1) w w 2
TRACE PROPERTY mn(nl) l l 2
TRACE PROPERTY mn(nl) w w 2
TRACE PROPERTY mn(n) l l 2
TRACE PROPERTY mn(n) w w 2
TRACE PROPERTY mn(n2) l l 2
TRACE PROPERTY mn(n2) w w 2
TRACE PROPERTY m(y) l l 2
TRACE PROPERTY m(y) w w 2
TRACE PROPERTY m(c1) l l 2
TRACE PROPERTY m(c1) w w 2
TRACE PROPERTY mn(nd) l l 2
TRACE PROPERTY mn(nd) w w 2
TRACE PROPERTY mn(nz) l l 2
TRACE PROPERTY mn(nz) w w 2
TRACE PROPERTY mn(nn) l l 2
TRACE PROPERTY mn(nn) w w 2
TRACE PROPERTY m(c2) l l 2
TRACE PROPERTY m(c2) w w 2
TRACE PROPERTY mp(pz) l l 2
TRACE PROPERTY mp(pz) w w 2
TRACE PROPERTY mp(pd) l l 2
TRACE PROPERTY mp(pd) w w 2
TRACE PROPERTY mp(p) l l 2
TRACE PROPERTY mp(p) w w 2
TRACE PROPERTY mp(ps) l l 2
TRACE PROPERTY mp(ps) w w 2
TRACE PROPERTY mp(pm) l l 2
TRACE PROPERTY mp(pm) w w 2
TRACE PROPERTY q(nv) a a 0
TRACE PROPERTY q(pv) a a 0
TRACE PROPERTY d(dp) a a 0
TRACE PROPERTY d(dw) a a 0
TRACE PROPERTY d(dn) a a 0
TRACE PROPERTY r(lr) r r 2
TRACE PROPERTY r(m5) r r 0
TRACE PROPERTY r(ns) r r 0
TRACE PROPERTY r(m4) r r 0
TRACE PROPERTY r(wo) r r 0
TRACE PROPERTY r(pi) r r 0
TRACE PROPERTY r(nd) r r 0
TRACE PROPERTY r(m1) r r 0
TRACE PROPERTY r(pd) r r 0
TRACE PROPERTY r(nr) r r 0
TRACE PROPERTY r(pr) r r 0
TRACE PROPERTY r(m3) r r 0
TRACE PROPERTY r(ps) r r 0
TRACE PROPERTY r(ni) r r 0
TRACE PROPERTY r(m2) r r 0
TRACE PROPERTY r(wr) r r 0
TRACE PROPERTY rppolywo_rf l l 0
TRACE PROPERTY rppolywo_rf w w 0
TRACE PROPERTY pmos_rf33w5 lr lr 0
TRACE PROPERTY pmos_rf33w5 wr wr 0
TRACE PROPERTY pmos_rf33w5 nr nr 0
TRACE PROPERTY nmos_rf33w5 lr lr 0
TRACE PROPERTY nmos_rf33w5 wr wr 0
TRACE PROPERTY nmos_rf33w5 nr nr 0
TRACE PROPERTY pmos_rfw10 lr lr 0
TRACE PROPERTY pmos_rfw10 wr wr 0
TRACE PROPERTY pmos_rfw10 nr nr 0
TRACE PROPERTY xjvar n n 0
TRACE PROPERTY xjvar pj pj 0
TRACE PROPERTY xjvar a a 0
TRACE PROPERTY rppoly_rf l l 0
TRACE PROPERTY rppoly_rf w w 0
TRACE PROPERTY mimcap lt lt 0
TRACE PROPERTY mimcap m m 0
TRACE PROPERTY mimcap a a 0
TRACE PROPERTY mimcap pj pj 0
TRACE PROPERTY spiral_turn nr nr 0
TRACE PROPERTY spiral_turn rad rad 0
TRACE PROPERTY spiral_turn w w 0
TRACE PROPERTY spiral_turn s s 0
TRACE PROPERTY nmos_rf33w10 lr lr 0
TRACE PROPERTY nmos_rf33w10 wr wr 0
TRACE PROPERTY nmos_rf33w10 nr nr 0
TRACE PROPERTY nmos_rfw10 lr lr 0
TRACE PROPERTY nmos_rfw10 wr wr 0
TRACE PROPERTY nmos_rfw10 nr nr 0
TRACE PROPERTY pmos_rfw5 lr lr 0
TRACE PROPERTY pmos_rfw5 wr wr 0
TRACE PROPERTY pmos_rfw5 nr nr 0
TRACE PROPERTY moscap a a 0
TRACE PROPERTY moscap pj pj 0
TRACE PROPERTY moscap n n 0
TRACE PROPERTY nmos_rftrw10 lr lr 0
TRACE PROPERTY nmos_rftrw10 wr wr 0
TRACE PROPERTY nmos_rftrw10 nr nr 0
TRACE PROPERTY nmos_rfw5 lr lr 0
TRACE PROPERTY nmos_rfw5 wr wr 0
TRACE PROPERTY nmos_rfw5 nr nr 0
TRACE PROPERTY pmos_rf33w10 lr lr 0
TRACE PROPERTY pmos_rf33w10 wr wr 0
TRACE PROPERTY pmos_rf33w10 nr nr 0
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances (see below).
LAYOUT CELL NAME: delete
SOURCE CELL NAME: delete
--------------------------------------------------------------------------------------------------------------
NUMBERS OF OBJECTS
------------------
Layout Source Component Type
------ ------ --------------
Ports: 3 3
Nets: 3 3
Instances: 0 1 * MN (4 pins)
1 0 * nmos_rfw5 (4 pins)
------ ------
Total Inst: 1 1
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 X0(10.380,12.380) nmos_rfw5 ** missing instance **
--------------------------------------------------------------------------------------------------------------
2 ** missing instance ** MNM0 MN(N)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 3 3 0 0
Nets: 3 3 0 0
Instances: 0 0 0 1 MN(N)
0 0 1 0 nmos_rfw5
------- ------- --------- ---------
Total Inst: 0 0 1 1
o Initial Correspondence Points:
Ports: G D S
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec
原理图还是没识别管子类型，好奇怪啊
自己顶一下，呵呵
你认为管子的类型到底哪个是对的? MN还是nmos_rfw5?
应该nmos_rfw5是对的，我调用管子的时候都是这个类型滴啊，可能是哪里出了问题呢?
那就是说产生CDL的过程出错了. CDL的结果是直接由CDF参数决定的. 你先看看原理图中调用的那个晶体管的CDF参数是怎么设置的,比如netlist procedure之类的。如果代工厂的PDK所带的SKILL初始化文件没有load进来，也会在CDL上面出错。你看看加载你们工艺库子目录下的libInit.il文件有没有效果。
9#正解，是CDL不一致导致；
你看电路symbol显示时的model和LVS做的model是不一样的；其差异可参考cadence下<<CDF.....>>手册的说明；
如果是安装的PDK，就要像9#那样，load一个skill文件；
如果是自己做的基本库，可考虑在Cadence-->tool---->CDF里面手动修改cdf参数
恩啊，非常感谢，呵呵，我先试试
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