Input offset simulation

1. Your comparator has gain stage and latch stage.
2. You can not see DC offset at latch stage, because it is saturated at VDD or GND.
3. Set your clock high to let the latch stage in driving mode. (clk=H, driving mode; clk=L, latch mode)
4. You do AC simulation  to get voltage gain of your gain stage output.
5. You do DC simulation and do Monte-Carlo simulation. Short gain stage input to let zero input offset. Check gain stage output DC offset voltage for 3 sigma.
6. (output offset)/(voltage gain)=(input offset)
7. You do not worry "how about the offset of latch stage?". Your gain stage offset dominates total offset, because your gain stage voltage gain >20.

very good

good！

不錯的訊息
謝謝分享

解释的很详细啊

不錯的資訊
感謝樓主分享

申明：网友回复良莠不齐，仅供参考。如需专业解答，请学习本站推出的微波射频专业培训课程。